"

中国足球协会杯赛直播---中国足彩网(yb3548.cn)是亚洲优质游戏品牌,综合各种在线游戏于一站式的大型游戏平台,经营多年一直为大家提供安全稳定的游戏环境,中国足球协会杯赛直播---中国足彩网值得信赖,期待广大游戏爱好者前来体验,中国足球协会杯赛直播---中国足彩网将把最好的游戏体验带给大家!

                              "
                              • 焦海龍

                              • 職稱:副教授
                              • 電話:0755-26035580;辦公室:A-320
                              • Email:jiaohailong@pku.edu.cn
                              • 實驗室網站:http://www.PKU-VLSI.com
                              研究方向:低功耗高可靠性超大規模集成電路與系統設計。

                                  焦海龍,博士,北京大學深圳研究生院副教授,博士生導師。2004年于山東大學獲得電子信息科學與技術專業學士學位,2008年于中國科學院微電子研究所獲得微電子學與固體電子學碩士學位,2012年于香港科技大學獲得電子及計算機工程學博士學位。2013年9月加入荷蘭埃因霍溫理工大學電子工程系,任職Tenure-track Assistant Professor,2016年9月獲得終身教職。2015年2月起,兼任比利時魯汶微電子中心(IMEC)三維集成部門訪問研究員。2017年1月全職加入北京大學深圳研究生院信息工程學院。焦海龍博士現任Elsevier Microelectronics Journal (MEJ)及World Scientific Journal of Circuits, Systems, and Computers (JCSC)編委,并長期擔任如ISVLSI, SOCC, ASP-DAC等多個IEEE/ACM國際會議的技術委員會成員。

                                  焦海龍博士的主要研究方向為低功耗高可靠性超大規模集成電路與系統設計,重點關注超低電壓電路設計、容錯系統設計、近似計算、存內計算、機器學習在超大規模集成電路中的應用、三維集成電路設計、柔性電子學、碳基電子學等。已在相關領域發表國際期刊及會議論文70余篇。 

                              ?要研究成果:

                              ?書籍章節

                              [1]   H. Jiao and V. Kursun, “Tri-Mode Operation for Noise Reduction and Data Preservation in Low-Leakage Multi-Threshold CMOS Circuits,” VLSI-SoC: Forward-Looking Trends in IC and System Design, J. L. Ayala, D. A. Atienza, and R. Reis, (Eds.), Springer, pp. 258-290, 2012, ISBN 978-3-642-28565-3.

                              ?期刊論文 (* Corresponding author; ^ Supervised student as first author)

                              [1]   H.-M. Lam, F. Guo, H. Qiu, M. Zhang, H. Jiao*, and S. Zhang, “Pseudo Multi-Port SRAM Circuit for Image Processing in Display Drivers,” IEEE Transactions on Circuits and Systems for Video Technology, 2020.

                              [2]   X. Huo^, C. Liao, M. Zhang, H. Jiao*, and S. Zhang, “A Pixel Circuit With Wide Data Voltage Range for OLEDoS Microdisplays With High Uniformity,” IEEE Transactions on Electron Devices, Vol. 66, No. 11, pp. 4798-4804, November 2019.

                              [3]   Y. Sun, W. He, Z. Mao, H. Jiao*, and V. Kursun, “A High-Yield and Robust 9T SRAM Cell Tolerant to Removal of Metallic Carbon Nanotubes,” IEEE Transactions on Device and Materials Reliability, Vol. 17, No. 1, pp. 20-31, March 2017.

                              [4]   H. Jiao and V. Kursun, “Reactivation Noise Suppression with Sleep Signal Slew Rate Modulation in MTCMOS Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 3, pp. 533-545, March 2013.

                              [5]   H. Jiao and V. Kursun, “Threshold Voltage Tuning for Faster Activation with Lower Noise in Tri-Mode MTCMOS Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 4, pp. 741-745, April 2012.

                              [6]   H. Jiao and V. Kursun, “Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 5, pp. 763-773, May 2011.

                              [7]   H. Jiao and V. Kursun, “Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits,” IEEE Transactions on Circuits and Systems I, Vol. 57, No. 8, pp. 2053-2065, August 2010.

                              ?代表性國際會議論文 (* Corresponding author; ^ Supervised student as first author)

                              [1]   H. Jiao and Z. Zhang, “A Compact Low-Power Data Retention Flip-Flop with Easy-Sleep Mode,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2020.

                              [2]   P. Detterer^, C. Erdin, J. Huisken, H. Jiao, M. Nabi, T. Basten, J. Pineda de Gyvez, “Trading Sensitivity for Power in an IEEE 802.15.4 Conformant Adequate Demodulator,” Proceedings of the IEEE/ACM Conference on Design, Automation and Test in Europe (DATE), March 2020.

                              [3]   K. Singh^, B. de Bruin, J. Huisken, H. Jiao, and J. Pineda de Gyvez, “Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation,” Proceedings of the IEEE International SoC Conference (SOCC), pp. 370-375, September 2019.

                              [4]   X. Huo^, W. Bai, H.-M. Lam, C. Liao, M. Zhang, S. Zhang, and H. Jiao*, “A Compact Low-Voltage Segmented D/A Converter with Adjustable Gamma Coefficient for AMOLED Displays,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May 2019.

                              [5]   P. Detterer^, C. Erdin, M. Nabi, J. Pineda de Gyvez, T. Basten, and H. Jiao*, “Trading Digital Accuracy for Power in an RSSI Computation of a Sensor Network Transceiver,” Proceedings of the IEEE/ACM Conference on Design, Automation and Test in Europe (DATE), pp. 102-107, March 2019.

                              [6]   L. Katselas^, A. Hatzopoulos, H. Jiao, C. Papameletis, and E. J. Marinissen, “Embedded Toggle Generator to Provide Realistic Test Conditions during Test of Digital 2D-SoCs and 3D-SICs,” Proceedings of the IEEE International Test Conference (ITC), pp. 1-9, October 2018.

                              [7]   F. Hu^, M. Zhang, and H. Jiao*, “Achieving Low Power Classification with Classifier Ensemble,” Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 16-21, July 2018.

                              [8]   Y. Li^, M. Shao, H. Jiao, A. Cron, S. Bhatia, and E. J. Marinissen, “IEEE Std P1838’s Flexible Parallel Port and its Specification with Google’s Protocol Buffers,” Proceedings of the IEEE European Test Symposium (ETS), pp. 1-6, May 2018.

                              [9]   K. Singh^, O. A. Rodriguez Rosas, H. Jiao, J. Huisken, and J. Pineda de Gyvez, “Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May 2018.

                              [10]  K. Singh^, H. Jiao, J. Huisken, H. Fatemi, and J. Pineda de Gyvez, “Low Power Latch Based Design with Smart Retiming,” Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design (ISQED), pp. 329-334, March 2018.

                              [11]  M. van Leussen^, J. Huisken, L. Wang, H. Jiao*, and J. Pineda de Gyvez, “Reconfigurable Support Vector Machine Classifier with Approximate Computing,” Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2017.

                              [12]  H. Ahmadi Balef^, H. Jiao, J. Pineda de Gyvez, and K. Goossens, “An Analytical Model for Interdependent Setup/Hold-Time Characterization of Flip-flops,” Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design (ISQED), pp. 209-214, March 2017.

                              [13]   E. J. Marinissen, T. McLaurin, and H. Jiao, “IEEE Std P1838: DfT Standard-under-Development for 2.5D-, 3D-, and 5.5D-SICs,” Proceedings of the IEEE European Test Symposium (ETS), May 2016.

                              [14]   Y. Sun, H. Jiao, and V. Kursun, “Low-Leakage 9-CN-MOSFET SRAM Cell with Enhanced Read and Write Voltage Margins,” Proceedings of the IEEE International Conference on Microelectronics (ICM), pp. 164-167, December 2014 (Best Paper Award).

                              [15]   H. Jiao and V. Kursun, “Ground Gated 8T SRAM Cells with Enhanced Read and Hold Data Stability,” Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 52-57, August 2013.

                              [16]   S. M. Salahuddin, H. Jiao, and V. Kursun, “A Novel 6T SRAM Cell with Asymmetrically Gate Underlap Engineered FinFETs for Enhanced Read Data Stability and Write Ability,” Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design (ISQED), pp. 353-358, March 2013.

                              [17]   H. Jiao and V. Kursun, “Multi-Phase Sleep Signal Modulation for Mode Transition Noise Mitigation in MTCMOS Circuits,” Proceedings of the IEEE International SoC Design Conference (ISOCC), pp. 466-469, November 2012 (SoC Design Group Award).

                              [18]   H. Jiao and V. Kursun, “Sleep Signal Slew Rate Modulation for Mode Transition Noise Suppression in Ground Gated Integrated Circuits,” Proceedings of the IEEE International SoC Conference (SOCC), pp. 365-370, September 2011.

                              對計劃招收研究生的基本要求:

                              1.  Self-motivated(成功需要的是你個人的追逐,而非導師的鞭策);

                              2.  卓越的邏輯思維能力及動手能力;

                              3.  良好的英語聽說讀寫能力;

                                  實驗室關注同學們的個人發展,致力于培養同學們成為具有獨立研究能力及獨立工程開發能力的科研工作者或者工程師。實驗室同時將盡力為同學提供芯片tapeout機會(65-nm/55-nm/28-nm CMOS工藝),詳情參見實驗室網頁 http://www.PKU-VLSI.com。

                              ?

                              中国足球协会杯赛直播---中国足彩网